1. Field of the Invention
The present invention relates to a circuit arrangement for sequentially outputting data bits of a selected word read out from a memory cell array.
2. Description of the Related Art
According to a prior art memory readout circuit which is shown in FIG. 1, a memory cell array 1 stores 256-bit words of data. In response to a read enable pulse from a read/write controller 6,256 bits of a word is simultaneously transferred by a transfer gate array 2 to a data register 3 which is connected to a transfer gate array 4. The latter is divided equally into upper and lower groups of 128 transfer gates and each group is further divided into 32 subgroups of 4 transfer gates each, so that the transfer gates of each subgroup store first to fourth data bits as a unit of data to be transferred. The transfer gates of the upper group are connected respectively to data buffers 7 and those of the lower group are connected respectively to data buffers 8. In response to an address signal from read/write controller 6, a unit data selector 5 alternately selects upper and lower groups of transfer gate array 4 and identifies one of the subgroups of the selected group to cause the transfer gates of the identified subgroup to transfer the data bits stored therein to corresponding data buffers. A gate array 9 is provided for reading data bits from data buffers 7 and 8 onto an external circuit via a buffer amplifier 11 in response to control signals from a data bit selector 10 which responds to an address signal from controller 6.
While high speed reading is possible, the alternate reading of upper and lower groups of data prevents data from being read in sequence from the same group. Additionally, the use of two set of data buffers adds extra complexity and hardware.